1. Field of the Invention
The present invention generally relates to a method and apparatus for measurement of electrical properties in a semiconductor wafer, and more particularly, to the measurement of the electrical properties of a dielectric layer on a semiconductor wafer.
2. Discussion of the Related Art
The determination of electrical properties of a dielectric layer on a semiconductor wafer body is a critical factor in the production of such wafers as is well known in the art. Measurements such as dielectric rupture voltage, dielectric field strength, time dependent dielectric breakdown and oxide charge measurements, for example, are typically accomplished by first fabricating metal or doped polysilicon mesas over the dielectric layer that serve as electrical contacts to which measurement probes may be applied. The metal mesas or dots, together with the dielectric layer and substrate, form a metal-oxide-semiconductor (MOS) structure. Fabrication of the metal mesas is a time-consuming and costly operation. It typically involves the selective evaporation of aluminum metal dots onto the dielectric or oxide layer, as well as the evaporation of a blanket aluminum layer on the back of the wafer. With respect to the latter, any oxide on the back side of the wafer must first be stripped from the back side of the wafer before the back side aluminum evaporation. Generally, a metal mask with an array of various size apertures is positioned immediately in front of the wafer to determine where dots will be formed during aluminum evaporation. A sintering and alloying process is then completed to reduce interface states charge at the oxide/silicon interface and to reduce contact resistance between the back side aluminum and silicon. Another disadvantage of this technique is its invasiveness within the wafer structure, resulting in inaccuracies being introduced in electrical measurements.
In addition to the above, MOS Capacitance-Voltage (C-V) measurements are very useful for fixed, mobile, and surface states charge characterization; however, for a variety of charge measurement requirements, the conventional MOS method can be prohibitively expensive and inconvenient. For MOS charge measurements on monitor wafers, sample preparation typically includes frontside aluminum dots and backside blanket aluminum. Such sample preparation is costly, time consuming and destructive. In addition, for MOS charge monitoring on product wafers, a highly desirable feature, such as being able to test arbitrary locations at almost any stage of processing, is not a practical possibility.
In U.S. Pat. No. 5,023,561, entitled "Apparatus and Method For Non-invasive Measurement of Electrical Properties of a Dielectric Layer in a Semiconductor Wafer", assigned to Solid State Measurements, Inc., and issued on Jun. 11, 1991, an apparatus is disclosed which includes a probe tip having a uniformly flat contact portion. The metal probe of the '561 patent is used for contacting a dielectric layer on a wafer in order to obtain C-V measurements for dielectric charge determinations. To liken, but still distinguish, the use of a probe electrode for "MOS like" measurements from MOS, the term Probe-Oxide-Semiconductor (hereinafter "POS") will be used throughout the text of this specification. The geometry and operating conditions of the '561 metal POS probe includes an extremely flat geometry and a relatively low, non-deforming pressure on the order of 10 psi., the low pressure being a proper pressure for avoiding damage of the test sample surface. The flat geometry of the '561 metal POS probe presents a sharp edge, which if excessive force were applied to the probe in contacting the dielectric, would increase the probability for damage and cracking to occur in the dielectric layer. For an increasingly thin dielectric layer range, on the order of 10-50 nm (100-500 .ANG.), presently being used in CMOS technologies, the '561 metal POS probe is not well suited. For example, in the instance of a 10 nm thick dielectric, the effective air gap between the '561 probe tip and the dielectric surface would need to be less than 0.3 nm for a C-V characteristic to have less than a 10% error. This would be difficult to achieve, even with a perfectly flat probe, since 0.3 nm could be on the order of the surface roughness of the oxide or dielectric layer under test. To compensate for any surface roughness using the '561 probe, a higher pressure may be applied to close up any small air gaps; however, the resultant stress near the sharp edge of the flat probe greatly increases the likelihood of surface damage to the test sample. Additionally, the '561 POS test probe involves a polishing process, not subject to high repeatability, for use in making the same, and thus results in increased variations between probes.
There is thus needed an improved method and apparatus well suited for obtaining MOS C-V measurements, absent the problems, difficulties, and limitations, as discussed above.